all: puresim

VLOG = \
	hdl/params_pkg.sv \
	hdl/interface.sv \
	hdl/controller.sv \
	hdl/memory_stub.sv \
	hdl/top.sv
	
SVLOG = \
	hdl/params_pkg.sv \
	hvl/ddr3_assertions.sv \
	hvl/testbench_hvl.sv

puresim:
	vlib puresim_work
	vmap work puresim_work 
	vlog -f $(TBX_HOME)/questa/hdl/xtlm_files.f
	vlog $(SVLOG)
	vlog $(VLOG)
	tbxsvlink -puresim
	vsim -novopt top testbench_hvl TbxSvManager
	
veloce:
	vlib tbx_work
	vmap work tbx_work
	vlog -f $(TBX_HOME)/questa/hdl/xtlm_files.f
	vlog $(SVLOG)
	tbxcomp -top top $(VLOG) -veloce
	tbxsvlink -veloce


